Probe card

ABSTRACT

The present invention provides a probe card comprising a circuit board, a plurality of electrodes, and a plurality of probes. The electrodes are provided on the circuit board. One ends of the probes are respectively connected to the electrodes, and the other ends thereof are floating for testing chips. The present invention is characterized in that the electrodes can be longitudinally parallel, transversely parallel, or slantingly parallel arranged so that good layout of wiring can be achieved, sequential wiring can be obtained, and the problems of wire jumping or cutting can be avoided. Therefore, it is easy to perform maintenance, and the debugging time can be reduced.

FIELD OF THE INVENTION

[0001] The present invention relates to a probe card and, more particularly, to an improved electrode structure on a circuit board. By means of novel arrangement of the present invention, wiring can be accomplished in duplicate manner, layout and debugging can be easily performed, and working efficiency can be enhanced.

BACKGROUND OF THE INVENTION

[0002] In the prior art, a probe card is provided on a detection head of a specially designed IC tester for testing a chip. The structure of the probe card is shown in FIGS. 1 and 2, wherein a plurality of circularly arranged electrodes 2 a are provided on a circuit board 1 a. The electrodes 2 a are respectively connected to one ends of thin probes 3 a made of gold wires. The other ends of the probes 3 a are floating and can be used to detect pads 6 a of a chip 5 a on a wafer 4 a so as to input signals to the chip 5 a or detect output values from the chip 5 a. By controlling an electron microscope and a machine arm, all chips 5 a on the same wafer 4 a can be tested one by one.

[0003] However, the following problems are often generated when connecting the probes 3 a:

[0004] 1. Wire cutting or jumping is often required to manufacture sequential wiring (shown in FIG. 3).

[0005] 2. Wrong soldering after wire jumping usually occurs so as to increase the production time and cost.

[0006] 3. Electrical characteristics cannot be exactly followed so that the difficulty of duplication is increased.

[0007] 4. Debugging time is increased.

[0008] 5. It is hard to perform on-line maintenance.

SUMMARY OF THE INVENTION

[0009] To resolve the above problems in the prior art, the primary object of the present invention is to change the arrangement manner of the electrodes from circular arrangement to parallel arrangement so as to avoid complicated wiring. Thereby, it is easy to connect the probes, and the manufacturing efficiency can be greatly enhanced.

[0010] To achieve the above object, the present invention provides a probe card comprising a circuit board, a plurality of electrodes, and a plurality of probes. The electrodes are provided on the circuit board and are parallel arranged. One ends of the probes are respectively connected to the electrodes, and the other ends thereof are floating and can be used to test chips.

[0011] The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a perspective view of a prior art probe card;

[0013]FIG. 2 is a plan view of a prior art probe card;

[0014]FIG. 3 is a plan view of a prior art probe card requiring wire cutting or jumping.

[0015]FIG. 4 is a plan view of the present invention laid out to connect a chip C1;

[0016]FIG. 5 is a plan view of the present invention laid out to connect all chips;

[0017]FIG. 6 is a plan view of a second embodiment of the present invention;

[0018]FIG. 7 is a plan view of a third embodiment of the present invention; and

[0019]FIG. 8 is a plan view of a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] A probe card of the present invention is shown in FIGS. 4 and 5, wherein 256 longitudinally and parallel arranged electrodes 2 (respectively designated electrode 0˜electrode 255) are provided on a circuit board 1. The electrodes 2 are respectively connected to one ends of the probes 3. The other ends of the probes 3 are floating. Chips 4 (respectively designated C1˜C8) on a wafer (not shown) are tested in parallel processing manner.

[0021] Fourteen electrodes 2 of the electrodes 0˜17 can be first selected to connect the probes 3 so that the other ends of the probes 3 correspond to fourteen pads 5 of the chip C1 to be tested. Next, fourteen electrodes 2 of the electrodes 32˜49 are selected to connect the probes 3 so that the other ends of the probes 3 correspond to fourteen pads 5 of the chip C2 to be tested. The above connection way is repeated so that good layout of wiring can be achieved, conventional problems of wire cutting or jumping can be avoided, and debugging can be easily performed.

[0022] Additionally, FIG. 6 shows a second embodiment of the present invention, wherein thirty two pads 5 are provided on the chip 4. Similarly, thirty two electrodes 2 can be selected from the electrodes 0˜49 to respectively connect the probes 3 so that the other ends of the probes 3 correspond to thirty two pads 5 of the chip C1 to be tested. Next, thirty two electrodes 2 of the electrodes 64˜144 are selected to connect the probes 3 so that the other ends of the probes 3 correspond to thirty two pads 5 of the chip C2 to be tested. The above connection way is repeated so that good layout of wiring can be achieved. Therefore, a user can select a probe card having a proper number of electrodes 2 for testing according to the number of the pads 5 of the chip 4 to be tested.

[0023] Furthermore, FIGS. 7 and 8 respectively show a third embodiment and a fourth embodiment of the present invention, wherein the electrodes 2 are longitudinally parallel arranged or slantingly parallel arranged. The connection way of the probes 3 is the same as above. In the fourth embodiment of the present invention, the chips 4 are tested in manner of parallel processing and sideway testing to match the arrangement of the chips 4 on a wafer.

[0024] To sum up, the probe card of the present invention has the following characteristics.

[0025] 1. The wiring is unambiguous.

[0026] 2. The manufacturing time of the probe card is shortened.

[0027] 3. The count of parallel processed chips is increased.

[0028] 4. Because it is easy to follow the electrical characteristics and it is easy to write the software, the production time can be greatly reduced so as to increase the efficiency and production.

[0029] 5. The testing cost of mass-produced chips is reduced.

[0030] Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims. 

I claim:
 1. A probe card comprising: a circuit board; a plurality of electrodes provided on said circuit board, said electrodes being parallel arranged; and a plurality of probes with one ends thereof connected to said electrodes and the other ends thereof floating for testing a chip; whereby good layout of wiring can be achieved when connecting said probes, and the problems of wire jumping or cutting can be avoided.
 2. The probe card as claimed in claim 1, wherein said electrodes are longitudinally parallel arranged.
 3. The probe card as claimed in claim 1, wherein said electrodes are transversely parallel arranged.
 4. The probe card as claimed in claim 1, wherein said electrodes are slantingly parallel arranged. 